| 摘要 |
<p>An encoding circuit for converting successive bits of original data to successive bits of coded data at a coding rate equal to m/n, where m and n are each an integer satisfying m<n, in accordance with a rule of a run-length-limited coding system, containing an encoder which inputs parallel m bits of the original data, and outputs parallel n bits of coded data corresponding to the input. Successive bits of data which are to be encoded are cyclically divided into a plurality of groups, and the data in the plurality of groups are input in a plurality of shift registers (116, 117), respectively. Each of the plurality of shift registers (116, 117) simultaneously supplies a part of the m bits of the input to the encoder, synchronizing with a clock. The above n bits of the output of the encoder is received in parallel in another shift register (121), and are serially output from the shift register (121), synchronizing with another clock. A decoding circuit for converting successive bits of coded data to successive bits of original data at a coding rate equal to m/n in accordance with the rule of the run-length-limited coding system, containing a decoder which inputs parallel n bits of the coded data, and outputs parallel m bits of the original data corresponding to the input. Successive bits of coded data which is to be decoded are serially input into a shift register (84), and the n bits of the input to the decoder (85) are supplied in parallel from the shift register (84) to the decoder (85). The m bits of the output of the decoder (85) are cyclically divided into a plurality of shift registers (87, 88), and the original data is obtained in parallel from the plurality of shift registers (87, 88).</p> |
