Circuit arrangement for driving of a MOS field-effect transistor.

摘要

A circuit arrangement for gate-controlling a MOS field-effect transistor (To) comprises a discharge circuit (12) via which the charge stored in the gate-source capacitance (CGS) can be discharged according to a time constant, the value of which depends on the internal impedance of said discharge circuit (12). This discharge circuit (12) can be switched between two conditions determined by a relatively large and a relatively small internal impedance respectively and assumes the condition dictated by the relatively small internal impedance as soon as the gate-source voltage (UGS) has dropped below a predetermined limit. <IMAGE>