发明名称 |
Path analyzing displaying apparatus for designing logic circuit |
摘要 |
The invention provides a path analyzing displaying apparatus for designing a logic circuit which can achieve reduction in intervention degree of a designer and expansion of human interface with a minimum portion which requires intervention. The apparatus comprises a graphic screen for displaying information necessary for path analysis of a logic circuit of an object of designing. Logic circuit components are grouped into a target group including a noticed point determined based on a logical simulation output result and any of the logic circuit components which can have an influence on the noticed point and a non-target group which includes those logic circuit components which do not have an influence on the analysis point, and the graphic screen displays the logic circuit components separately in the target group and the non-target group. The apparatus is applied to design a logic circuit of an LSI, a PCB or the like.
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申请公布号 |
US5754442(A) |
申请公布日期 |
1998.05.19 |
申请号 |
US19950505964 |
申请日期 |
1995.07.24 |
申请人 |
FUJITSU LIMITED |
发明人 |
MINAGAWA, EIJI;URAGUCHI, HISASHI |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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