发明名称 |
Process for manufacturing a MOS-technology power device chip and package assembly |
摘要 |
A process for manufacturing a MOS-technology power device chip and package assembly, the MOS-technology power device chip comprises a semiconductor material layer in which a plurality of elementary functional units is integrated, each elementary functional unit contributing a respective fraction to an overall current and including a first doped region of a first conductivity type formed in the semiconductor layer, and a second doped region of a second conductivity type formed inside the first doped region; the package comprises a plurality of pins for the external electrical and mechanical connection; the plurality of elementary functional its is composed of sub-pluralities of elementary functional units, the second doped regions of all the elementary functional units of each sub-plurality being contacted by a same respective metal plate electrically insulated from the metal plates contacting the second doped regions of all the elementary functional units of the other sub-pluralities; each of the metal plates are connected, through a respective bonding wire, to a respective pin of the package.
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申请公布号 |
US5851855(A) |
申请公布日期 |
1998.12.22 |
申请号 |
US19970795697 |
申请日期 |
1997.02.04 |
申请人 |
SGS-THOMSON MICROELECTRONICS S.R.L.;CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO |
发明人 |
FERLA, GIUSEPPE;FRISINA, FERRUCCIO |
分类号 |
H01L21/60;H01L21/768;H01L23/12;H01L23/482;H01L23/495;H01L23/522;H01L29/417;H01L29/78;(IPC1-7):H01L21/265;H01L49/00 |
主分类号 |
H01L21/60 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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