| 摘要 |
PROBLEM TO BE SOLVED: To provide an instruction controller which executes efficient and high speed operation control with less hardware even when an address depending relation is generated between a preceding storage instruction and a subsequent fetch request especially in an information processor having a reservation station on the instruction controller. SOLUTION: This instruction controller is provided with a reservation station 22 having a flag showing a storage instruction, a table showing that the source operand of the instruction stored in the reservation station 22 can be used, and an instruction issuing control means 23 for issuing the instruction from the reservation station 22 when the table shows that the source operand can be used, and making the fetch request of the subsequent instruction stand by until the address calculation and the request of the storage instruction completes when the flag detects the issuing of the storage instruction.
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