Multi-level tracking of in-use state of cache lines

摘要

This disclosure includes tracking of in-use states of cache lines to improve throughput of pipelines and thus increase performance of processors. Access data for a number of sets of instructions stored in an instruction cache may be tracked using an in-use array in a first array until the data for one or more of those sets reach a threshold condition. A second array may then be used as the in-use array to track the sets of instructions after a micro-operation is inserted into the pipeline. When the micro-operation retires from the pipeline, the first array may be cleared. The process may repeat after the second array reaches the threshold condition. During the tracking, an in-use state for an instruction line may be detected by inspecting a corresponding bit in each of the arrays. Additional arrays may also be used to track the in-use state.

主权项

1. A computer-implemented method comprising:
pointing an array selector to a first array; tracking an in-use state of a plurality of instructions in the first array until the tracked in-use state of the plurality of instructions reaches a threshold condition; redirecting the array selector to a second array; inserting a marker operation into a pipeline; tracking another in-use state of the plurality of instructions in the second array at least while the marker operation is in the pipeline; clearing the in-use state of the plurality of instructions in the first array in response to retirement of the marker operation from the pipeline; and allocating an entry storage in the plurality of instructions based at least in part on the in-use state tracked by the first and second arrays.