Display link clocking method and apparatus

摘要

An apparatus includes a clock circuit and a plurality of display interface circuits. The clock circuit provides a common clock signal. The display interface circuits each provide a respective display link clock signal in response to the common clock signal. One of the display link clock signals is at a different clock speed that another of the display link clock signals.

主权项

1. An apparatus comprising:
a clock circuit that is operative to provide a common clock signal synthesized from a reference clock signal; and a plurality of display interface circuits that are operative to provide a plurality of respective display link clock signals in response to the common clock signal, wherein a first of the plurality of display link clock signals is at a different clock speed than the common clock signal while a second of the plurality of display link clock signals is simultaneously at a different clock speed than both the first of the plurality of display link clock signals and the common clock signal, wherein the clock speeds of the first and second of the plurality of display link clock signals are adjusted in response to display configuration information from each of a first and a second of a plurality of displays respectively for simultaneously driving the first and the second of the plurality of displays respectively.