Switched capacitor DC-DC converter with reduced in-rush current and fault protection

摘要

To reduce in-rush currents into a switched capacitor DC/DC converter and detect voltage and current faults, a converter controller is housed along with a current limit series transistor and fault detection circuitry. The series transistor is controlled to limit the in-rush current to a predetermined maximum level during start-up. If the duration of the current limit level, or the time for Vout to achieve a target voltage, exceeds a first threshold time, a first fault detector in the package shuts off the series transistor. During steady state operation, if the input current reaches the limit for a second threshold time or if Vout extends outside a certain range for the second threshold time, a second fault detector in the package shuts off the series transistor.

主权项

1. A circuit for controlling a switched capacitor DC/DC converter to generate an output voltage Vout comprising:
a controller circuit for generating control signals for controlling switches in the switched capacitor DC/DC converter to generate Vout; an input terminal for an input voltage Vin1; an input current sensor for generating an input current signal corresponding to an input current; a current limit circuit coupled to the input current sensor for detecting when the input current has reached a current limit level and for controlling in-rush current into the converter so as not to exceed the current limit level, wherein the current limit circuit controls the in-rush current so as not to exceed a predetermined maximum current level; a series transistor coupled between the input terminal and the converter; a series transistor controller for controlling the series transistor to limit the in-rush current into the converter to the current limit level during start-up when Vin1 is applied to the input terminal; a fault detection circuit comprising:
a first fault circuit for detecting whether there is an input current fault or a Vout fault during a start-up phase of the circuit and for turning off the series transistor if a fault is detected during the start-up phase; and a second fault circuit for detecting whether there is an input current fault or a Vout fault during a steady state phase of the circuit and for turning off the series transistor if a fault is detected during the steady state phase.