| 发明名称 | Digital to analog converter, unit for the same, and method for using the same | ||
| 摘要 | Disclosed herein is a digital-to-analog converter (DAC) including a clock driver for controlling a clock signal to provide an inverse delay clock signal to allow at least selective adjustment of a return to zero (RZ) section; and a DAC core comprising at least two DAC units for receiving a digital input value, the clock signal and the inverse delay clock signal and providing an analog output value. According to the present invention, distortion of the output of the DAC may be attenuated and loss of the output may be minimized by utilizing the RZ technique. | ||
| 申请公布号 | US9520892(B2) | 申请公布日期 | 2016.12.13 |
| 申请号 | US201514979521 | 申请日期 | 2015.12.28 |
| 申请人 | GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGY | 发明人 | Lee Min-Jae;Kim Seong-Geon;Kang Jae-Hyun |
| 分类号 | H03K5/14;H03K3/356;H03M1/66;H03M1/06 | 主分类号 | H03K5/14 |
| 代理机构 | Hauptman Ham, LLP | 代理人 | Hauptman Ham, LLP |
| 主权项 | 1. A digital-to-analog converter (DAC) comprising: a clock driver for controlling a clock signal to provide an inverse delay clock signal to allow at least selective adjustment of a return to zero (RZ) section; and a DAC core comprising at least two DAC units for receiving a digital input value, the clock signal and the inverse delay clock signal and providing an analog output value. | ||
| 地址 | Gwangju KR | ||