Synchronous burst semiconductor memory device

摘要

A synchronous burst semiconductor memory device (300) with a pipelined multi-bit prefetch architecture includes separate intemal address generators (310,314) for respective read and write burst modes. The synchronous memory device (300) also adopts an auto-tracking bit line scheme to reduce core cycle time, a shortened main data line for current reduction, a noise immune circuit having high-speed transfer characteristics through a dual-rail reset dynamic circuit, and strobe clocks synchronized with the output data to guarantee processor data-validation time. <IMAGE>