发明名称 |
Semiconductor memory device |
摘要 |
A semiconductor memory device adapted for avoiding collision between the selection period of a word line for a refresh and the selection period of a word line for a read/write, comprises a cell array including a plurality of memory cells that require refreshing for retention of storage data and means for exercising control so that when a read/write request is input in a clock cycle following a clock cycle for performing a refresh operation, a read/write operation in the cell array is delayed by at least one clock cycle, and the read/write operation is started after completion of the refresh.
|
申请公布号 |
US2005041520(A1) |
申请公布日期 |
2005.02.24 |
申请号 |
US20040920249 |
申请日期 |
2004.08.18 |
申请人 |
NEC ELECTRONICS CORPORATION |
发明人 |
TAKAHASHI HIROYUKI;HIROTA TAKUYA |
分类号 |
G11C8/18;G11C11/403;G11C11/406;G11C11/407;(IPC1-7):G11C7/00;G11C8/00 |
主分类号 |
G11C8/18 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|