Configurable multi-lane scrambler for flexible protocol support

摘要

Various structures and methods are disclosed related to configurable scrambling circuitry. Embodiments can be configured to support one of a plurality of protocols. Some embodiments relate to a configurable multilane scrambler that can be adapted either to combine scrambling circuits across a plurality of lanes or to provide independent lane-based scramblers. Some embodiments are configurable to select a scrambler type. Some embodiments are configurable to adapt to one of a plurality of protocol-specific scrambling polynomials. Some embodiments relate to selecting between least significant bit (“LSB”) and most significant bit (“MSB”) ordering of data. In some embodiments, scrambler circuits in each lane are adapted to handle data that is more than one bit wide.

主权项

1. A configurable scrambler in an integrated circuit (“IC”) for supporting a plurality of scrambling polynomial functions, the configurable scrambler comprising:
a plurality of shift register elements at least equal in number to a highest exponent value for a term within the plurality of scrambling polynomial functions; and programmable taps fewer in number than the plurality of shift register elements, the programmable taps coupled between each output of a subset of the plurality of shift register elements and a feedback XOR circuit tree, wherein the programmable taps are configurable to select between each of the plurality of scrambling polynomial functions, and wherein the feedback XOR circuit tree includes a plurality of XOR circuits, the plurality of XOR circuits including at least a first XOR circuit and a second XOR circuit, the first XOR circuit being coupled to receive respective XOR inputs from respective different ones of the programmable taps and the second XOR circuit being coupled at one of its XOR inputs to an XOR output of the first XOR circuit.