NOC loopback routing tables to reduce I/O loading and off-chip delays

摘要

Technologies are generally described to implement loopback simulation of inter-core messages in multicore processors. In some examples, a multicore processor may execute one or more processes, where each process communicates with other processes on or off the processor. Messages originating from processes on the multicore processor and destined for other processes on the multicore processor may be intercepted by a loopback simulator executing on the multicore processor. The loopback simulator may then redirect the intercepted messages to the destination processes on the multicore processor without the messages leaving the multicore processor.

主权项

1. A method for on-chip loopback in multicore processors, the method comprising:
identifying one or more processes on a multicore processor, wherein the processes are adapted to communicate with each other via an off-chip network; and generating a simulated network loopback at a processor hardware layer to deliver messages between the one or more processes without using the off-chip network, wherein generating the simulated loopback comprises:
generating a core-process-to-IP-address map;identifying a destination core for a message based on the core-process-to-IP-address map;identifying data associated with the message to be delivered to the identified destination core; andprocessing the identified data back into one or more on-chip flits to be delivered to the identified destination core.