| 发明名称 | Method for protecting a cryptographic device against SPA, DPA and time attacks | ||
| 摘要 | A method is for operating a cryptographic device to reduce effects of power analysis and time attacks. The method may include executing a first set of cryptographic algorithm computations with a first crypto-processor of the cryptographic device. The first set of cryptographic algorithm computations may provide encryption of a first set of data to be protected with a first secret key stored in the cryptographic device. The method may further include executing a second set of cryptographic algorithm computations with a second crypto-processor of the cryptographic device for providing encryption of a second set of data different from the first set of data to be protected with a second different secret key. | ||
| 申请公布号 | US9430188(B2) | 申请公布日期 | 2016.08.30 |
| 申请号 | US200912649567 | 申请日期 | 2009.12.30 |
| 申请人 | STMICROELECTRONICS INTERNATIONAL N.V. | 发明人 | Di Sirio Giovanni;Fontana Giovanni |
| 分类号 | H04L29/06;G06F7/00;H04L9/00 | 主分类号 | H04L29/06 |
| 代理机构 | Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A. | 代理人 | Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A. |
| 主权项 | 1. A method of operating a cryptographic device to reduce effects of power analysis attacks, the method comprising: splitting cryptographic computations in the cryptographic device into a first set of cryptographic algorithm computations and a second set of cryptographic algorithm computations and pseudo-randomly assigning the first and second sets of cryptographic algorithm computations to a first crypto-processor and at least one second crypto-processor; executing the first set of cryptographic algorithm computations with the first crypto-processor of the cryptographic device, the first set of cryptographic algorithm computations providing encryption of a first set of data to be protected with a first secret key; executing the second set of cryptographic algorithm computations with the at least one second crypto-processor of the cryptographic device for providing encryption of a second set of data different from the first set of data to be protected with a second different secret key; and generating varying power consumption from the first crypto-processor and the at least one second crypto-processor respectively based upon the execution of the first and second sets of cryptographic algorithm computations, thereby reducing the effects of power analysis attacks. | ||
| 地址 | Geneva CH | ||