发明名称 |
Semiconductor device having stressor and method of fabricating the same |
摘要 |
A semiconductor device may include a fin active region including a lower fin active region surrounded by a device isolation layer and an upper fin active region protruding from a top surface of the device isolation layer, a gate pattern disposed on top and side surfaces of the upper fin active region, and a source/drain region formed in the fin active region located at a side of the gate pattern. The gate pattern extends onto the device isolation region. The source/drain region includes a trench and epitaxial layers that fill the trench. Sidewalls of the trench include first sidewalls and second sidewalls that connect the first sidewalls to a bottom surface of the trench. The bottom surface of the trench is located at a lower level than the top surface of the device isolation layer beneath the gate pattern, and the second sidewalls of the trench have inclined {111} planes. |
申请公布号 |
US9466721(B1) |
申请公布日期 |
2016.10.11 |
申请号 |
US201514978155 |
申请日期 |
2015.12.22 |
申请人 |
Samsung Electronics Co., Ltd. |
发明人 |
Kim Jinbum;Lee Kwanheum;Kang Hyunjae;Koo Bonyoung;Kim Seokhoon;Moon Kanghun;Park Jaeyoung;Lee Byeongchan;Lee Sunyoung;Lee Choeun;Lee Hanki;Jung Sujin;Xu Yang |
分类号 |
H01L27/088;H01L29/78;H01L29/417;H01L29/06;H01L29/423;H01L29/10 |
主分类号 |
H01L27/088 |
代理机构 |
Harness, Dickey & Pierce |
代理人 |
Harness, Dickey & Pierce |
主权项 |
1. A semiconductor device comprising:
a fin active region including a lower fin active region surrounded by a device isolation layer and an upper fin active region that protrudes from a top surface of the device isolation layer; a gate pattern on top and side surfaces of the upper fin active region, and extending above the device isolation layer; and a source/drain region in the fin active region at a side of the gate pattern, wherein the source/drain region includes a trench and epitaxial layers filling the trench,
wherein the trench includes a bottom surface and sidewalls,
wherein the sidewalls include first sidewalls and second sidewalls, the second sidewalls connecting the first sidewalls to the bottom surface,the bottom surface of the trench at a lower level than the top surface of the device isolation layer under the gate pattern, andthe second sidewalls of the trench have inclined {111} planes. |
地址 |
Gyeonggi-do KR |