| 摘要 |
1522958 Semiconductor devices FAIRCHILD CAMERA & INSTRUMENT CORP 8 Sept 1975 [29 Oct 1974] 36831/75 Heading H1K In oxide-isolated semiconductor devices, in particular integrated injection logic devices comprising a lateral and a vertical complementary bipolar transistor, prior to the formation of an oxide in a groove 14, Fig. 5B, formed in a silicon epitaxial layer 12, Fig. 5D, on a silicon substrate 10 of a conductivity type opposite to that of the epitaxial layer 12, an impurity is selectively applied to the groove defining the device region so as to form in subsequent oxidation of the groove a guard ring 30, 32, 33 of a conductivity type opposite to that of the epitaxial layer in the device region everywhere along the interface of the oxide-isolation region and the device region except adjacent the base region of the lateral bipolar transistor and except adjacent the emitter contact of the complimentary vertical transistor. This is achieved by forming a selfaligned silicon-dioxide base mask 17 over the boundary of the base of the lateral transistor (PNP) with the groove and over the boundary of the groove with the emitter contact region of the vertical transistor (NPN) prior to the oxidation of the groove and diffusion of the guard ring P-type impurity. The emitter region (35), Fig. 6 (not shown) of the lateral PNP and the base region (36) of the vertical NPN are formed in a single ionimplantation step using standard photo-masking techniques. Similarly, collector regions (37a, 37b), Fig. 7 (not shown) and emitter contact region (38) of the vertical NPN are formed in a single ion-implantation or diffusion step, this being followed by further doping of P- type impurity in the emitter region (35) and the base region (36) to provide a heavily doped emitter region (35) and a base contact (40), Fig. 8 (not shown). In a modified integrated injector logic device, the base region of the vertical NPN comprises high concentration P-type sub-regions (61, 62, 63), Fig. 15 (not shown), alternated with low-concentration P- type sub-regions (65, 66) thereby improving the # of both the transistors. A buried region 11 of the conductivity type same as that of the epitaxial layer may be provided. It is stated that the guard ring optimizes the # of both the transistors. In place of an integrated injection logic device, FETs, Schottky devices &c. may be formed.
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