发明名称 |
Microprocessor supporting variable length instruction execution |
摘要 |
<p>A microprocessor is provided for supporting reduction of codes in size, wherein instructions are extended in units of 0.5 word from a basic one word code. A word of instruction, fetched from an external memory, is transferred to a decoding register via instruction buffers and a selector both operate in units of half words, then is decoded by a decoder. A storage unit stores a state of an instruction stored in an instruction buffer. A controlling unit controls the selector so that the instructions are transferred from instruction buffers to the decoding register in units of half words based on a direction from the decoder and the states stored in the storage unit.</p> |
申请公布号 |
EP0745932(A2) |
申请公布日期 |
1996.12.04 |
申请号 |
EP19960303914 |
申请日期 |
1996.05.30 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
MATSUZAKI, TOSHIMICHI;DEGUCHI, MASASHI;HAMAGUCHI, TOSHIFUMI;TANASE, YUTAKA;MATSUMOTO, MASAHIKO |
分类号 |
G06F9/30;G06F9/318;G06F9/38;(IPC1-7):G06F9/30 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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