| 摘要 |
A pipelined superscalar processor comprises two or more pipelines that include decode, operand read, execute and writeback stages. An instruction datapath includes a plurality of result buses (17-19) coupled to a corresponding plurality of write ports (U, MLU, V) of a register file (20), which also has a plurality of read ports (U1-U2 and V1-V2). The read ports (U1-U2 and V1-V2) are coupled to the multiplexers (27-30) which select operands for various operations specified by one or more instructions. The results of the operations are then provided on the result buses (17-19). A bypass mechanism (22-23 and 25) allows a result produced during the execute stage to be bypassed to the read stage of a subsequent instruction which specifies the result as a source operand. |
