发明名称 SEMICONDUCTOR WAFER PROCESSOR AND ALIGNMENT METHOD IN SEMICONDUCTOR WAFER PROCESSOR
摘要 <p>PROBLEM TO BE SOLVED: To contrive to save a space taking into consideration an arrangement space of an alignment mechanism and a cooling mechanism and to obtain a device capable of simplifying maintenance works by a method wherein the alignment mechanism is arranged in an downward portion of a conveying passage for conveying a semiconductor wafer and the cooling mechanism is arranged in an upward portion of the conveying passage, etc. SOLUTION: This embodiment comprises a conveying passage 4 for conveying semiconductor wafers W, and alignment means 6 to 14 which are arranged in a downward portion of the conveying portion 4 to support the conveyed wafers W and correct an angle slippage and a position slippage of the wafers W. This embodiment further comprises cooling means 25 which is arranged in an upward portion of the conveying passage 4 and arranged in a counter position of the alignment means 6 to 14 to cool the wafers W. For example, the alignment means 6 to 14 detect an edge position of the wafer W by rotation of a rotor 6, rotate and displace the wafers W together with a lift mechanism 9 from detection signals detecting a position slippage amount and a slippage angle of the wafer W, and align the center of the rotor 6 to the center of the wafer W.</p>
申请公布号 JPH09213770(A) 申请公布日期 1997.08.15
申请号 JP19960013034 申请日期 1996.01.29
申请人 TOSHIBA CORP 发明人 FURUYA MASAAKI
分类号 H01L21/68;(IPC1-7):H01L21/68 主分类号 H01L21/68
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