发明名称 |
DIGITAL QUADRATURE MODULATOR AND DIGITAL QUADRATURE DEMODULATOR |
摘要 |
PROBLEM TO BE SOLVED: To provide the circuit configuration not requiring an arithmetic circuit executing multiplication of exp(jωst) required for digital quadrature modulation/ demodulation. SOLUTION: A 2K-th tap of a roll off filter coefficient of a (4N-1)-tap designed on the basis of 4fs is assigned to an acyclic digital filter 3 and a (2K+1)-th tap is assigned to an acyclic digital filter 4 and a sign of the tap coefficients of the digital filters 3, 4 is inverted at an interval of one. A multiplexer circuit applies time division multiplex to outputs of the digital filters 3, 4 alternately to provide an output of the result. Thus, the arithmetic operation of convolution of the digital filters is executed simultaneously at the arithmetic operation for modulation and demodulation. |
申请公布号 |
JPH09181786(A) |
申请公布日期 |
1997.07.11 |
申请号 |
JP19950338530 |
申请日期 |
1995.12.26 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
JINNO IPPEI;SAKASHITA SEIJI;HAYASHI DAISUKE |
分类号 |
H03H17/00;H03H17/06;H04L27/34 |
主分类号 |
H03H17/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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