发明名称 DEVICE FOR TESTING SEMICONDUCTOR INTEGRATED CIRCUIT AND ITS METHOD AND METHOD FOR ADJUSTING TIMING AND METHOD FOR ADJUSTING TEST VECTOR ADDRESS
摘要 PROBLEM TO BE SOLVED: To realize a device for testing a semiconductor integrated circuit for realizing the reinforcement or extension of a testing function without operating any reinforcement or extension of a new function at the testing device. SOLUTION: Plural testing devices are connected with a semiconductor integrated circuit 5, and a clock output synchronizing circuit 11 of a master device 1A is connected with an outside clock synchronizing circuit 12 of a slave device 1B. Then, the transmission and reception of a test vector with the semiconductor integrated circuit 5 is operated in a state that the master device 1A is synchronized with the slave device 1B by controlling operation control signal inputting circuits 14 and operation control signal outputting circuits 13 of the master device 1A and the slave device 1B. Thus, it is possible to perform the test by complementing a function which is short in a single testing device 1.
申请公布号 JP2000180515(A) 申请公布日期 2000.06.30
申请号 JP19980362617 申请日期 1998.12.21
申请人 NEC CORP 发明人 CHIKOU KENTA;AOYAMA SHINTARO
分类号 G01R31/28;G01R31/3183;(IPC1-7):G01R31/28;G01R31/318 主分类号 G01R31/28
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