发明名称 |
Semiconductor memory device which controls sense amplifier for detecting bit line bridge and method of controlling the semiconductor memory device |
摘要 |
In a sense amplifier control circuit and method for a semiconductor memory device, a row address strobe (RAS) signal delay unit delays a RAS signal for a predetermined period of time. A sense amplifier control signal generator generates first and second sense amplifier control signals, responsive to the delayed RAS signal and a test mode control signal, which are enabled at the same time or at different periods depending on operation modes of the memory device. First and second sense amplifiers respectively sense and amplify the potential of odd-numbered and even-numbered bit line pairs of the memory device, responsive to the first and second sense amplifier control signals. The probability and accuracy of detecting bit line bridge defects are increased, because the times for sensing two adjacent bit lines are different.
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申请公布号 |
US6396754(B1) |
申请公布日期 |
2002.05.28 |
申请号 |
US20010901050 |
申请日期 |
2001.07.10 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
LEE HYONG-YONG;JUN SUK-BAE;PARK CHOONG-SUN |
分类号 |
G01R31/28;G11C11/401;G11C11/409;G11C29/02;G11C29/12;(IPC1-7):G11C29/00 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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