| 发明名称 | Digital phase-locked loop (DPLL), method of controlling DPLL, and ultra low power (ULP) transceiver using DPLL | ||
| 摘要 | A phase-locked loop (PLL) includes a counter configured to measure voltage-controlled oscillator (VCO) information of an oscillator during a mask time, and a frequency tuner configured to tune a frequency of the oscillator to a target frequency, based on a comparison result obtained by comparing the VCO information to target frequency information. | ||
| 申请公布号 | US9413369(B2) | 申请公布日期 | 2016.08.09 |
| 申请号 | US201514600533 | 申请日期 | 2015.01.20 |
| 申请人 | Samsung Electronics Co., Ltd. | 发明人 | Kim Seong Joong;Yun Seok Ju;Hong Young Jun;Park Hyung Gu;Lee Kang Yoon |
| 分类号 | H03D3/24;H03L7/099;H04B1/40 | 主分类号 | H03D3/24 |
| 代理机构 | NSIP Law | 代理人 | NSIP Law |
| 主权项 | 1. A phase-locked loop (PLL), comprising: a counter configured to measure voltage-controlled oscillator (VCO) information of an oscillator during a mask time; and a frequency tuner configured to tune a frequency of the oscillator to a target frequency, based on a comparison result obtained by comparing the VCO information to target frequency information, wherein, in response to the frequency of the oscillator matching the target frequency, the PLL is configured to supply power to the frequency tuner to be used to maintain the frequency of the oscillator matching the target frequency. | ||
| 地址 | Suwon-si KR | ||