Multiple V_Tin III-V FETs

摘要

In one aspect, a method of forming a multiple VT device structure includes the steps of: forming an alternating series of channel and barrier layers as a stack having at least one first channel layer, at least one first barrier layer, and at least one second channel layer; defining at least one first and at least one second active area in the stack; selectively removing the at least one first channel/barrier layers from the at least one second active area, such that the at least one first channel layer and the at least one second channel layer are the top-most layers in the stack in the at least one first and the at least one second active areas, respectively, wherein the at least one first barrier layer is configured to confine charge carriers to the at least one first channel layer in the first active area.

主权项

1. A multiple VT device structure, comprising:
an alternating series of channel layers and barrier layers in a stack on a side of a BOX opposite a substrate, wherein the stack comprises at least one first channel layer present over at least one first barrier layer, and at least one second channel layer present below the at least one first barrier layer, wherein the at least one first channel layer comprises a first III-V material and the at least one second channel layer comprises a second III-V material, and wherein the first III-V material has a different electron affinity from the second III-V material; at least one first active area and at least one second active area defined in the stack, wherein the at least one first channel layer is a top-most layer in the stack in the at least one first active area, and the at least one second channel layer is a top-most layer in the stack in the at least one second active area, wherein the at least one first barrier layer is configured to confine charge carriers to the at least one first channel layer in the first active area; at least one first gate on the at least one first channel layer in the at least one first active area; and at least one second gate on the at least one second channel layer in the at least one second active area, wherein the at least one first channel layer serves as a channel of a first FET in the at least one first active area, and the at least one second channel layer serves as a channel of a second FET in the at least one second active area, and wherein the first FET has a different VT from the second FET based on the different electron affinity between the first III-V material and the second III-V material.