发明名称 Semiconductor device
摘要 To provide a semiconductor device that has a novel structure and achieves a higher degree of convenience, the semiconductor device is configured to include a memory cell that stores binary data or multilevel data, and a reading circuit that reads the data stored in the memory cell and transfers the data to the outside. The reading circuit includes a first reading circuit for reading binary data and a second reading circuit for reading multilevel data.
申请公布号 US9437273(B2) 申请公布日期 2016.09.06
申请号 US201314139248 申请日期 2013.12.23
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 Yamazaki Shunpei;Koyama Jun
分类号 G11C16/26;G11C11/405;G11C11/4076;G11C11/56 主分类号 G11C16/26
代理机构 Fish & Richardson P.C. 代理人 Fish & Richardson P.C.
主权项 1. A semiconductor device comprising: a switch; a bit line electrically connected to a first terminal of the switch; a word line; a memory cell electrically connected to the bit line and the word line; a first comparator electrically connected to a second terminal of the switch; a second comparator electrically connected to a third terminal of the switch; and a third comparator electrically connected to the third terminal of the switch, wherein the memory cell is configured to store binary data or multilevel data, wherein the binary data is supplied from the bit line to the first comparator through the switch when the binary data is read from the memory cell, wherein the multilevel data is supplied from the bit line to the second comparator through the switch when the multilevel data is read from the memory cell, wherein the multilevel data is supplied from the bit line to the third comparator through the switch when the multilevel data is read from the memory cell, wherein the first comparator is configured to compare a level of a first reference voltage and a voltage corresponding to the binary data read from the memory cell, wherein the second comparator is configured to compare a level of a second reference voltage and a voltage corresponding to the multilevel data read from the memory cell, and wherein the third comparator is configured to compare a level of a third reference voltage and the voltage corresponding to the multilevel data read from the memory cell.
地址 Atsugi-shi, Kanagawa-ken JP