| 摘要 |
<p>PURPOSE:To improve speed for a read only IC memory by arranging Y decode signal wiring between the elements of a logically constituted Y selector and arranging the high-order Y selector element closely to a sense amplifier load circuit. CONSTITUTION:When the sense amplifier load of a memory cell array is con nected by the Y selector in the AND constitution of two steps, a Y selector 2 in the second step is arranged close to a sense amplifier 1 and Y decode signal wirings 3 and 4 are arranged between the selector 2 and a Y selector 5 in the first step. Then, output data signal connecting wiring 7 is connected between the selectors 2 and 5 so as to cross the wirings 3 and 4. Thus, wiring capacity for a part crossing the wirings 3 and 4 is attached to a connecting point between the selectors 2 and 5. Wiring capacity to be attached to the other selector in the second step is not always the capacity to be driven by the sense amplifier load circuit 1 separated by the Y selector. Accordingly, the wiring can be shortened between the sense amplifier load and Y selector and the speed for the read only IC memory is improved.</p> |
