发明名称 |
Delayed locked loop clock generator using delay-pulse-delay conversion |
摘要 |
A delayed locked loop (DLL) clock generator in DDR SDRAM is disclosed. The DLL clock generator comprises a pulse generator for generating a pulse signal of which a pulse width corresponds to a predetermined delay time; a first delay chain including a plurality of delay means, for delaying the pulse signal by a predetermined delay time in order; and a second delay chain having the same delay time as the first delay chain, for delaying an external clock signal responsive to an output signal from the delay means. The second clock signal is generated through the same path as a path through which the external clock signal is inputted and the delayed external clock signal is outputted.
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申请公布号 |
US6342797(B1) |
申请公布日期 |
2002.01.29 |
申请号 |
US19990475226 |
申请日期 |
1999.12.30 |
申请人 |
HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. |
发明人 |
LEE SEONG-HOON |
分类号 |
G11C11/407;G06F1/10;G11C7/22;H03K5/13;H03K5/135;H03L7/00;H03L7/081;H04L7/033;(IPC1-7):H03L7/06 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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