| 摘要 |
<p>A gated clock scheme designing method for controlling a clock in a position as nearer the supply source of a clock supply path as possible. The method is characterized in that clock control signals are so merged into one group that clock control signal used for giving instructions to supply/stop clocks to registers in a n integrated circuit and having the periods for which the clocks are stopped overlap with one another for longer times, the OR of the clock control signals belonging to the same group is used as a group control signal, a gated clock buffer receiving the group control signals are disposed in the clock supply paths to the registers in one group.</p> |
