| 摘要 |
A system and method for finding electromigration (EM), self heat (SH) and voltage drop/droop violations of an integrated circuit, when its design and electrical characterization are not complete, are disclosed. The method includes analyzing polygons for average, root-mean-square (RMS) and Ipeak current densities and voltages of a mask layout block and obtaining one or more electromigration, self heat and/or voltage drop/droop rules associated with the polygon from a technology and an external constraints file. The system reads the available design simulation data to calculate the average, RMS and Ipeak current densities and voltages, and estimates the current densities and voltages when no data available. The method also includes topological analysis of the mask layout and analysis of the electrical circuit elements of the design. The method finds the polygons where the current densities are higher than electromigration and self heat rules as taken from technology or external constraints file. The method also finds the polygons where the current densities are higher than in other polygons, by the defined threshold. The method also finds the nodes where the voltage drop/droop is larger than the rule. The method also finds the polygons where the voltage drop/droop is larger than in other polygons by the defined threshold. The method and system work on GDSII, GDSIII format files and on industry standards layout editors' database.
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