GATE INPUT PROTECTON FOR DEVICES AND SYSTEMS COMPRISING HIGH POWER E-MODE GaN TRANSISTORS

摘要

An integrated gate protection device P for a GaN power transistor D1 provides negative ESD spike protection. Protection device P comprises a smaller gate width wg enhancement mode GaN transistor Pm. The source of Pm is connected to its gate, the drain of Pm is connected to the gate input of D1, and the source of Pm is connected to the intrinsic source of D1. When the gate input voltage is taken negative below the threshold voltage for reverse conduction, Pm conducts and quenches negative voltage spikes. When device P comprises a plurality of GaN protection transistors P1 to Pn, connected in series, it turns on when the gate input voltage applied to the drain of P1 goes negative by more than the sum of the threshold voltages of P1 to Pn. The combined gate width of P1 to Pn is selected to limit the gate voltage excursion of D1.

主权项

1. A GaN power switching device comprising a GaN power transistor D1 and an integrated gate protection device P for negative ESD spike protection,
the GaN power transistor D1 comprising an enhancement mode GaN power transistor of gate width Wg; the integrated gate protection device P comprising a GaN protection transistor Pm comprising an enhancement mode GaN transistor of smaller gate width wg, the gate of the GaN protection transistor Pm being connected to the source of the GaN protection transistor Pm, the drain of the GaN protection transistor Pm being connected to the gate input of the first GaN transistor, and the source of the GaN protection transistor Pm being connected to the intrinsic source of the GaN power transistor D1; wherein, the GaN protection device P being is normally off, and when a gate input voltage of the GaN power transistor D1 applied to the drain of the GaN protection transistor Pm is taken negative by more than the threshold voltage for reverse conduction of GaN protection transistor Pm, the protection device P conducts.