HIGH SPEED FPGA BOOT-UP THROUGH CONCURRENT MULTI-FRAME CONFIGURATION SCHEME

摘要

Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant reduction of configuration time. By enabling high-speed FPGA boot-up, the programmable integrated circuit device will be able to accommodate applications that require faster boot-up time than conventional programmable integrated circuit devices are able to accommodate. In order to enable high-speed boot-up, dedicated address registers are implemented for each data line segment of a data line, which in turn significantly reduces configuration random access memory (CRAM) write time (e.g., by a factor of at least two).

主权项

1. A programmable integrated circuit device, comprising:
a plurality of data line segments comprising configuration random access memory (CRAM), wherein each data line segment is configured to receive data via a pipeline column or a data register, wherein the respective pipeline column and the data register are configured to pipeline the data through a respective data line segment of the plurality of data line segments; and a plurality of address registers, wherein each address register of the plurality of address registers corresponds to a respective data line segment of the plurality of data line segments, and wherein a respective address register of the plurality of address registers is configured to activate when the data is propagated to a respective CRAM of a respective data line segment of the plurality of data line segments.