Variable Precision In Hardware Pipelines For Power Conservation

摘要

A digital signal processor includes a variable precision hardware pipeline that provides a maximum level of precision using a first plurality of bits for a mathematical representation. The pipeline stages include data registers to store the first plurality of bits. A precision select module selects a level of precision for processing a block of instructions and sets a precision control register. Logic circuitry utilizes the precision control register to gate the clock signal for one or more of the first plurality of bits to reduce the precision of the hardware pipeline. The logic circuitry disables the clock signal for the data latches in the pipeline corresponding to bits to be disabled to reduce the precision. By disabling the clock signal for the data registers, the amount of power consumed by the pipeline can be reduced.

主权项

1. A digital signal processing system, comprising:
a hardware pipeline including a clock signal and a set of data latches for storing a first plurality of bits in a first pipeline stage; a control register configured to select a precision of the hardware pipeline; control logic configured to determine for a plurality of data frames whether a full precision of the hardware pipeline can be reduced when processing each data frame, the control logic is configured to set the control register to select a reduced precision of the hardware pipeline in response to a determination that the full precision of the hardware pipeline can be reduced for one or more of the data frames; and one or more gates configured to disable the clock signal for one or more of the data latches of the hardware pipeline based on the control register when processing the one or more data frames.