| 摘要 |
<p>PURPOSE:To reduce the power consumption of a CPU by fixing a clock supplied to the CPU at a low level or a high level during a period of time before a ready signal from a storage part or an input/output part becomes active. CONSTITUTION:At the time of the normal operation of the CPU 10, the clock generated by a clock oscillating part 30 passes by a clock pulse width control means 50, and is supplied to the CPU 10. Next, in the case of access to the storage part 20, the start of a bus cycle is detected by a bus cycle detecting part 40 by monitoring the status of the CPU 10. Next, when the ready signal from the storage part 20 becomes active, the clock pulse width control means 50 starts the clock to the CPU 10, and supplies the clock 60 of an original cycle. At that time, it can be confirmed that the CPU 10 is ready by the start of the clock, the bus cycle in the course of execution is finished, and the next cycle is started. Thus, the power consumption in the CPU 10 can be reduced.</p> |
