发明名称 Data detection apparatus
摘要 <p>A reproduced signal is digitized so as to count a time interval of a specified pattern simultaneously with the count of a clock period of a phase lock loop circuit. A phase lock loop clock frequency is subjected to a feedback control based on the information indicating the difference between the time interval and the clock period. In this manner, a frequency loop performs a feedback operation so that a frequency of the reproduced signal falls within a capture range of a phase lock-in, thereby increasing the speed of phase lock-in. &lt;IMAGE&gt;</p>
申请公布号 EP0763825(A2) 申请公布日期 1997.03.19
申请号 EP19960114812 申请日期 1996.09.16
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 HORIBE, RYUSUKE;ISHIBASHI, HIROMITI;SHIMADA, TOSHIYUKI;MIYACHI, HIROYUKI
分类号 G11B20/14;G11B19/12;G11B27/30;H03L7/081;H03L7/089;H03L7/113;(IPC1-7):G11B20/14 主分类号 G11B20/14
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