发明名称 |
Communication method |
摘要 |
<p>The code system is realized by that a plurality of waveforms A and B each having duty ratios of 50% in which only any one of a rising edge and a falling edge is present are combined with each other, and "1" and "0" are allocated to the combined waveform. In accordance with the present invention, both a clock and data can be transmitted at the same time, and can be readily demodulated without using a complex PLL circuit. As a trial manufacture according to the present invention, the demodulator could be realized which could allow variations contained in an input frequency by more than 1 digit under operating voltage of 2 V. The effectiveness of this patent could be confirmed. <IMAGE></p> |
申请公布号 |
EP0967562(A2) |
申请公布日期 |
1999.12.29 |
申请号 |
EP19990110563 |
申请日期 |
1999.06.01 |
申请人 |
HITACHI, LTD. |
发明人 |
TANAKA, SATOSHI;ISHIFUJI, TOMOAKI;NAGAI, KENJI;FURUKAWA, KATSUHIRO |
分类号 |
H04L12/28;G06K17/00;G06K7/00;H04B5/02;H04L25/49;(IPC1-7):G06K7/00 |
主分类号 |
H04L12/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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