Level shifter and parallel-to-serial converter including the same

摘要

A level shifter circuit includes a level shifting unit configured to receive signals that may vary in a first range via a positive input terminal and a negative input terminal, respectively and to output signals that may vary in a second range to a positive output terminal and a negative output terminal, respectively, where the second range is larger than the first range, a first pre-charging unit configured to pre-charge the positive output terminal to a predetermined level when a clock is in a first level, and a second pre-charging unit configured to pre-charge the negative output terminal to the predetermined level when the clock is in the first level.

主权项

1. A level shifter, comprising:
a level shifting unit configured to receive a clock and one or more input signals having a first variable amplitude, and generate one or more output signals having a second variable amplitude, through an output terminal and a complementary output terminal respectively; a first pre-charging unit configured to receive a clock and pre-charge the output terminal by a pre-charging voltage having a predetermined level when the clock is in a first level; and a second pre-charging unit configured to receive a clock and pre-charge the complementary output terminal by the pre-charging voltage when the clock is in the first level wherein the first pre-charging unit includes:
a first inverter configured to invert an output signal from the output terminal to generate an inverted output signal;a first PMOS transistor configured to transfer an output of the first inverter to a first node when the clock is in the second level,a first NMOS transistor configured to drive the first node by a ground voltage level when the clock is in the first level,a second PMOS transistor configured to supply the pre-charging voltage when the clock is in the first level, anda third PMOS transistor configured to transfer the pre-charging voltage supplied through the second PMOS transistor to the output terminal under a control of the first node.