发明名称 CMOS clocked logic decoder
摘要 The present semiconductor logic circuit includes a first-stage logic circuit section comprising of a first precharging transistor, a first grounding transistor, and a first logic element and a second-stage logic circuit section comprising of a second precharging transistor, a second grounding transistor, and a second logic element. The first precharging transistor has the common terminal connected to a power terminal and receives a clock signal at the input terminal. The first grounding transistor has the common terminal connected to the ground and receives a clock signal at the input terminal. The first logic element has the grounding end connected to the output terminal of the first grounding transistor and the output end connected to the output terminal of the first precharging transistor. The second precharging transistor has the common terminal connected to a power terminal and the input terminal connected to the output end of the first logic element. The second grounding transistor has the common terminal connected to the ground and the input terminal connected to the output end of the first logic element. The second logic element has the grounding end connected to the output terminal of the second grounding transistor and the output end connected to the output terminal of the second precharging transistor.
申请公布号 US5258666(A) 申请公布日期 1993.11.02
申请号 US19920827359 申请日期 1992.01.29
申请人 NEC CORPORATION 发明人 FURUKI, KATSUYA
分类号 H03K19/017;H03K19/096;(IPC1-7):H03K19/094 主分类号 H03K19/017
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