发明名称 METHOD AND APPARATUS FOR GENERATION OF TEST PATTERN BY LOGIC CIRCUIT
摘要 PROBLEM TO BE SOLVED: To generate a test set in the small number of patterns in a short time. SOLUTION: A fault is selected by a fault selection part 113. Whenever the allocation of a signal value is changed by a signal-value change part 116, a control set is computed by a control-set computing part 124 so as to be stored in a control-set storage part 125. A present control set and a past control set are compared by a similarity judgment part so as the judge their similarity. When the similarity is judged to be high, the search of a decision tree is discontinued, and test pattern candidates are synthesized by a test-pattern-candidate synthesis part 132. By a test compression part 150, a test compression processing operation is executed to the set of the test pattern candidates obtained in this manner.
申请公布号 JPH1090375(A) 申请公布日期 1998.04.10
申请号 JP19960247443 申请日期 1996.09.19
申请人 HITACHI LTD 发明人 NATSUME KOICHIRO;HATAKEYAMA KAZUMI
分类号 G01R31/3183;G06F11/22 主分类号 G01R31/3183
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