| 摘要 |
PROBLEM TO BE SOLVED: To verify a semiconductor integrated circuit in timing during the course of failure detecting tests by latching the input value to a storage element from a combinational circuit other than the storage element in accordance with a prescribed clock change at and after the next time. SOLUTION: Each scan register 110-112 has a mode terminal M2 and can decide the timing between set data and the output data of the circuit corresponding to the set data. Mode terminals M2 are terminals for switching the mode to a test mode and, when the test mode is set, test data terminals TD and test clocks TCK operate and outputs the data obtained by performing prescribed logical operation, such as the inversion, etc., on held data at the first changing time of a clock CK when the clock CK changes two or more times. For a prescribed clock change at and after the second time, the input value to a storage element from a combinational circuit other than the storage element is latched. Therefore, a semiconductor integrated circuit can be verified in timing during the course of failure detecting tests. |
