发明名称 |
Combination field programmable gate array allowing dynamic reprogrammability and non-volatile programmability based upon transistor gate oxide breakdown |
摘要 |
A cell that can be used as a dynamic memory cell for storing data or a field programmable gate array (FPGA) cell for programming is disclosed. The cell includes a capacitor having a first terminal connected to a column bitline and a second terminal connected to a switch control node. A select transistor has a gate connected to the read bitline, a source connected to the switch control node, and a drain connected to a row wordline. The switch control node stores data as a voltage indicative of a one or a zero.
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申请公布号 |
US2005169039(A1) |
申请公布日期 |
2005.08.04 |
申请号 |
US20040782564 |
申请日期 |
2004.02.18 |
申请人 |
PENG JACK Z.;LIU ZHONGSHAN;YE FEI;FLIESLER MICHAEL D. |
发明人 |
PENG JACK Z.;LIU ZHONGSHAN;YE FEI;FLIESLER MICHAEL D. |
分类号 |
G11C11/24;G11C11/34;G11C11/401;G11C11/405;G11C11/406;G11C16/02;H01L21/8242;H01L27/02;H01L27/108;H01L27/118;H03K19/177;(IPC1-7):G11C11/34 |
主分类号 |
G11C11/24 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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