FAN -OUT WAFER LEVEL PACKAGING STRUCTURE

摘要

Described herein is a semiconductor device and the manufacturing method thereof, wherein the semiconductor device includes a first die including a first pad and a first passivation layer; a second die including a second pad and a second passivation layer; an encapsulant surrounding the first die and the second die and comprising a first surface; a dielectric layer covering at least a portion of the first passivation layer and at least a portion of the second passivation layer, and further covering the encapsulant between the first die and the second die, wherein the dielectric layer includes: a second surface adjacent to the first passivation layer, the second passivation layer and the encapsulant; and a third surface opposite to the second surface; and a redistribution layer electrically connecting to the first pad and the second pad and disposed above the third surface of the dielectric layer.

主权项

1. A semiconductor device, comprising:
a first die comprising a first pad and a first passivation layer; a second die comprising a second pad and a second passivation layer, wherein the first die has a first sidewall and the second die has a second sidewall; an encapsulant surrounding the first die and the second die and comprising a first surface; a dielectric layer covering at least a portion of the first passivation layer and at least a portion of the second passivation layer, and further covering the encapsulant between the first die and the second die, wherein the dielectric layer comprises:
a second surface adjacent to the first passivation layer, the second passivation layer and the encapsulant; anda third surface opposite to the second surface; and a redistribution layer electrically connecting to the first pad and the second pad and disposed above the third surface of the dielectric layer; wherein a first roughness of the first surface of the encapsulant is greater than a second roughness of the third surface of the dielectric layer.