Exposure process for structurising wafer with highly accurate control - by exposing position error mark in each field and correction before exposing circuit

摘要

Exposure process for transferring structures from a pattern contg. a circuit structure to a semiconductor wafer coated with a resist system and image field array, esp. in the prodn. of micro- or optoelectronic devices, uses a substrate table with highly accurate control in the planar co-ordinates x, y and psi; an opto-electronic alignment system, with measuring system(s) and regulating units, for aligning substrate marks and determining their substrate table co-ordinates; a projection system with light source and projection objective; and a l:x projection alignment and exposure device (PAE), pref. regulating the imaging scale for raising and lowering the substrate table. The resist-coated wafer is placed on the substrate table, the pattern is aligned with the marks on the wafer and the circuit structure is transferred by exposure with light of the required wavelength. After roughly aligning the wafer on the table by the alignment marks, the position is measured and the substrate co-ordinate system is ascertained, then the structure is transferred by carrying out a series of operations for each individual image field gp., involving: (a) entering the co-ordinates of at least one image field of an nth gp. in the series; (b) exposing the pattern region with position error measuring structures (PEMS), other measuring structures and alignment marks in at least 2 corners, with the circuit structure masked, so that the PEMS lie in the plane of the wafer, using light (La) of wavelength alpha to modify the reflectivity of the exposed areas by changing the deg. of absorption of the light (Lb) of wavelength beta used for measuring position errors; (c) entering the exposed PEMS in the input of the opto-electronic measuring system and measuring the position difference of the PEMS to the top-coat measuring structures produced on the wafer and/or in the resist system by structurisation and/or exposure with Lb, which does not alter the characteristics of the resist system; (d) determining the correction value for the x, y and psi co-ordinates giving min. position error, using a computer or the PAE; (e) entering the image field of the nth gp., with corrected values for the horizontal and vertical adjustments; and (f) exposing the circuit structure with La, the areas already exposed being masked. ADVANTAGE - The process gives optimum quality with very accurate exposed resist structures at low cost and high efficiency.