发明名称
摘要 PURPOSE:To prevent an even that frame synchronization is once confirmed, communication service is started and intermitted again by resetting the count of an error with cyclic code check for prescribed time with a guard timer signal when a signal path is selected. CONSTITUTION:When the input/output of a high order multiplexer is switched by a switcher or the like and a PCM input signal confirming circuit 15 confirms a PCM input signal, a timer circuit 16 is operated to send an error counter reset signal (guard time signal) 18 for a period when there are many errors in the PCM signal just after the input and output of the high order group multiplexer is switched to reset an error counter 8. When the predetermined period elapses, a timer circuit 16 completes output of the guard time signal. Then the reset of an error counter 8 is released to count the error.
申请公布号 JP2864530(B2) 申请公布日期 1999.03.03
申请号 JP19890121426 申请日期 1989.05.17
申请人 NIPPON DENKI KK 发明人 SUGA SEIICHI
分类号 H04J3/06;H04L7/00;H04L7/08 主分类号 H04J3/06
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