| 摘要 |
PROBLEM TO BE SOLVED: To provide an encryption processing apparatus having high resistance against DPA attack while suppressing increase in circuit scale. SOLUTION: In addition to a first register 103-1 and a second register 104-1, a third register 103-2 and a fourth register 104-2 are arranged. Data capture to respective registers 103-1, 103-2, 104-1, 104-2 is carried out with the same latch pulse Lat. A frequency dividing circuit 105 for dividing the frequency of the latch pulse Lat is provided. The data stored in the third register 103-2 and the fourth register 104-2 are the data obtained by performing an EXOR operation of the signals stored in the first register 103-1 and the second register 104-1 and a frequency divided signal DIV of the latch pulse Lat. An EXOR operation of register pairs - the first register 103-1 with the third register 103-2, and the second register 104-1 with the fourth register 104-2 - is performed. In the case other than whole-bit matching or whole-bit mismatching, reset signals RST1 and RST2 are generated, but the results of the mathematical operation are not output. COPYRIGHT: (C)2008,JPO&INPIT
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