发明名称 READING AND WRITING TO NAND FLASH MEMORIES USING CHARGE CONSTRAINED CODES
摘要 A charge constrained bit sequence is processed to obtain a lower bound on a number of bit errors associated with the charge constrained bit sequence. The lower bound is compared against an error correction capability threshold associated with an error correction decoder. In the event the lower bound is greater than or equal to the error correction decoder threshold, an error correction decoding failure is predicted.
申请公布号 US2016217034(A1) 申请公布日期 2016.07.28
申请号 US201615092110 申请日期 2016.04.06
申请人 SK Hynix Memory Solutions Inc. 发明人 Subramanian Arunkumar;Lee Frederick K.H.;Tang Xiangyu;Zeng Lingqi;Bellorado Jason
分类号 G06F11/10;G11C29/52 主分类号 G06F11/10
代理机构 代理人
主权项 1. A write processor, comprising: a first encoder configured to apply a charge constrained code to each unconstrained bit sequence in a set to obtain a first set of charge constrained bit sequences; a second encoder configured to independently and systematically error correction encode each charge constrained bit sequence in the first set to obtain a first set of parity sequences; a bit flipper configured to apply the charge constrained code to the first set of charge constrained bit sequences as a whole to obtain a second set of charge constrained bit sequences; a processor configured to process the first set of parity sequences to reflect the second set of charge constrained bit sequences to obtain a second set of parity sequences; and an interface configured to output the second set of charge constrained bit sequences and the second set of parity sequences.
地址 San Jose CA US