发明名称 HIGH-SPEED BUS SYSTEM
摘要 PROBLEM TO BE SOLVED: To provide a bus system that makes a memory-logic conjugate system function at high speed and with low power consumption.SOLUTION: Provided is a bus system for connecting functional blocks in a block chip with each other, with a plurality of functional blocks functioning as a memory circuit and/or a logic circuit arranged in array form in the block chip. The bus system includes an output control unit for controlling the destination of a data signal outputted from a functional block. The output control unit has an AND circuit 31 and a switch circuit 32. A clock signal and a selection signal are inputted to the AND circuit 31. The switch circuit 32 makes the data signal outputted via a first adjacent bus 33 when the AND circuit 31 is off, and makes the data signal branched off and outputted via the first adjacent bus 33 and a second adjacent bus 34 when the AND circuit 31 is on.SELECTED DRAWING: Figure 5
申请公布号 JP2016218619(A) 申请公布日期 2016.12.22
申请号 JP20150101079 申请日期 2015.05.18
申请人 NAGASE & CO LTD 发明人 OTSUKA KANJI;FUJII FUMIAKI;AKIYAMA YUTAKA;SATO YOICHI
分类号 G06F13/36;H03K19/177 主分类号 G06F13/36
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