发明名称 |
DIGITAL PHASE SYNCHRONOUS LOOP |
摘要 |
PURPOSE:To make a circuit scale for jitter suppression small by using a ring counter, which has a variable number of stages, or a variable frequency divider to rehlize phase control and frequency division for jitter reduction in the same circuit. |
申请公布号 |
JPS5399753(A) |
申请公布日期 |
1978.08.31 |
申请号 |
JP19770014407 |
申请日期 |
1977.02.12 |
申请人 |
NIPPON TELEGRAPH & TELEPHONE |
发明人 |
TATSUNO HIDEO;KAWASHIMA MAKOTO |
分类号 |
H03L7/06;H03K5/1252;H03K23/58 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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