Phase/frequency control loop has reset logic unit whose output signal is only activated/deactivated if both output signals of two edge-triggered memory units are activated/deactivated respectively

摘要

The arrangement has a phase/frequency comparator with two edge-triggered memory elements (13,14) and a reset logic unit (15) with inputs supplied by the outputs (9A,9B) of the memory units. The reset logic unit output signal is only activated if both output signals of the edge-triggered memory units are activated and only deactivated if both output signals of the edge-triggered memory units are deactivated. An independent claim is also included for the following: (a) a phase/frequency comparator.