发明名称 Memory array including isolation between memory cell and dummy cell portions
摘要 A semiconductor memory device structure includes an isolation region formed along an edge of a memory cell portion adjacent to a dummy cell portion to isolate the memory cell portion from leakage current generated in the dummy cell portion.
申请公布号 US7183608(B2) 申请公布日期 2007.02.27
申请号 US20050137476 申请日期 2005.05.26
申请人 MACRONIX INTERNATIONAL CO., LTD. 发明人 HUANG LAN-TING;LIU CHEN-CHIN;LIU CHENG JYE
分类号 H01L29/792 主分类号 H01L29/792
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