RECESS CHANNEL FLASH ARCHITECTURE FOR REDUCED SHORT CHANNEL EFFECT

摘要

A memory cell with reduced short channel effects is described. A source region (54) and a drain region (56) are formed in a semiconductor substrate (58). A trench region (59) is formed between the source region and the drain region. A recessed channel region (52) is formed below the trench region, the source region and the drain region. A gate dielectric layer (60) is formed in the trench region of the semiconductor substrate above the recessed channel region and between the source region and the drain region. A control gate layer (70) is formed on the semiconductor substrate above the recessed channel region, wherein the control gate layer is separated from the recessed channel region by the gate dielectric layer. ® KIPO & WIPO 2007